August
01 2004:
Welcome Back !
O.K, its time to put our Propeller Caps On :-)
With the sometimes break neck speed at which computer technology has
accelerated over the last few years, the focus has primarily remained
on CPU, Memory and Graphic Technologies. It may come as a surprise to
some that despite all of the advances, very little has changed in I/O
system technology since the introduction of the original PCI bus back
in the early 90’s. Audio Cards, USB, Firewire, LAN cards, etc,
all pass data through the same I/O system as your first 486 PC / Mac
7200, the PCI bus running at 33mhz and shifting 133MB/s of data. As
an example of recent technology, a current Pentium 4 with Dual Channel
DDR memory can shift 6.4 GB/s across the memory bus. The 8x AGP bus
can pass about 2.1GB/s of data a second. These are technologies developed
essentially to get around the limitations of the PCI.
So as you can see, the poor old PCI Bus was in desperate need of a turbo
boost. There have been various improvements to the PCI specifications
over the years, all designed to increase the amount of available bandwidth.
Some examples are 32 Bit and 64 Bit 66MHz PCI (266 /512 Mb Sec) up to
the recent introduction of PCI-X at 64bit/133MHz, (1066 Mb sec). However
all of these specifications are still limited by the same problems that
are inherent with all parallel I/O systems, in that the theoretical
bandwidth is being shared across the available PCI slots, so although
they are an improvement on the original PCI spec, that do not go far
enough in alleviating the bottlenecks that can occur with the ever increasing
demands placed on the I/O subsystem.
Enter PCI Express: Intel, in partnership with several other companies
which include the likes of IBM, Dell, Compaq, HP and Microsoft have
recently introduced what they hope will be the new standard for PC I/O
in the years to come; PCI-Express (formerly 3GIO or 3rd Generation I/O)
PCI-Express is intended to be an evolutionary as apposed to a revolutionary
upgrade to the existing PCI bus. It will maintain complete hardware
and software compatibility with all recent PCI devices. However, In
terms of actual form, i.e. slot compatibility, it is something completely
new.
PCIe’s most drastic and obvious improvement over
PCI is its point-to-point bus topology. Unlike with the previous system
where all of the devices would need to share the available bandwidth,
now each device sits on its own dedicated bus, which in PCIe lingo is
called a link. Each link is a 2-way serial connection that carries data
in packets; similar to the way it is transferred over Ethernet connections.
Each PCI Express X1 slot has its own dedicated bandwidth, which will
carry data upstream and downstream at 2.5Gb/s in each direction. The
PCI X16 slot, which will be the replacement for the current AGP standard,
performs at up to 4 GB sec, or nearly twice the 8X AGP's 2.1 GB sec.
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To make the transition as easy as possible,
the PCI-Express bus will be completely software compatible with PCI
2.2 compliant devices. Intel has already stated that all current operating
systems will support PCI 2.2 compatible interface cards in the new
PCI-Express system using the existing PCI drivers. Hooray for common
sense :-) If PCI-Express technology is to gain widespread acceptance,
fast tracking obsolescence will not be the way to win over the tech
community and end users. The days of the dreaded PCI bottleneck are
definitely on the way out :-)
Now lets move onto DDRII. Again DDRII is more
an evolutionary than a revolutionary step. Basically DDR-II can offer
double the overall memory bandwidth of DDR memory for the same speed
module by effectively using two DRAM cores per device instead of one
as used by DDR. Technically there is still only one DRAM core but
it is accessed in parallel allowing it to deal with 4 data pre-fetches
instead of two. This combined with data buffers running at double
data rate means that for each clock cycle up to 4-bits of data can
be dealt with instead of the 2-bits regular DDR can handle. The trade
off for this increase in bandwidth comes in the form of increased
latencies, the number of clock cycles certain operations take to be
carried out. CAS (Column Address Strobe) latency, is expected to rise
from 2 cycles as seen on current low latency modules to most likely
a minimum of 4 or 5 cycles for DDR-II. The end result is basically
that of increased bandwidth at the expense of latency.
Real World Performance has been less than spectacular with the early
benchmarks not showing any major performance advantage over the current
Dual Channel DDR configurations, but substantial improvements are
expected once the current latency issue can be addressed. The simple
fact that the new i915X and i925X chipsets support both DDR and DDR-II
means that Intel for now at least are not putting all of their eggs
in one basket. :-)
Add all of theses developments with the looming 64 bit landscape,
and the never ending CPU circus, and we can honestly say that, the
following months will be anything but boring.
Till next time :-)
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