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September 01 2004: Continuing our Journey: The Dual Core War is definitely
hotting up. Although realistically still a year away, all 3 chip giants
are thumping their chests in preparation of the battle to come. In my
last visit to the dual core arena I reported that Intel seemed to have
the jump on the field in regards to development, but in reality its
Cheapzilla (AMD) that appears to have the upper hand and Intel and IBM
are again finding themselves with their pants around their ankles, with
the pavement coming into focus at an amazing pace. :-) |
Chipzilla (Intel) is desperately trying to find their footing, as well as save face by talking up how advanced their Dual Core strategies are, but in reality its all a little bit of smoke and mirrors. These latest developments has brought focus to one of the main hurdles that Intel still need to address, which is their aging bus architecture. Intel has everything on a single shared bus, i.e., the CPUs and memory via the northbridge. If you have a single CPU, you effectively have a point to point link between the CPU and the northbridge. However Dual CPUs or Dual Cores for that matter, bring you a shared bus. The more CPUs you have, the more competition you have for the bus. Also, the higher the load, the lower the maximum bus speed you can get away with .The only way to get around it is to have each chip use the bus less. This is why you see MP Xeons utilising much larger caches. This solution tends to work well, but it requires the chips to have a much larger die area for those huge caches. Not an ideal situation if you’re trying to cram 2 cores onto a die. So with AMD’s dual core strategy
well along, Intel had to come up with something fast. The Answer is
a 2-prong attack? The primary one (Paxville / Smithfield) being totally
reactionary, with the real solution McCoy (Dempsey) to follow. The
first foray is simply two PIV cores bolted on to a chip, it appears
to the bus as two loads, and has all the associated problems with
two individual chips. On the up side, due to the fact that it has
a shared bus to begin with, there should be no loss of performance
over a dual chip setup. Still not exactly ideal though! Enter Dempsey.
Dempsey will be the first true dual core chip from Intel. The chips
main feature over the Paxville is bus arbitration logic in addition
to the second core. Instead of fighting for access to the bus, the
cores will talk to the arbitration logic, which will then fight for
the bus. In this way, the chip appears to be a single load on the
bus, giving you the best of both worlds. However ,the arbitration
will probably add a little latency, so you will have slightly worse
performance than two separate cores. Still, not a bad overall solution,
and done as right as can be on a shared bus. This will have to do
until the Intel introduces its new serial bus architecture (CSI )
. This will be introduced with the Conroe (Desktop) and Mermon (Mobile)
chips, which are based on the Pentium M Core. These were the chips
that started all of the traffic in relation to the End of Netburst
and the Megahertz Myth. It was initially thought that these chips
had been fast tracked to be released in the first half of 2005, but
as the latest roadmap suggest, this was no more than wishful thinking
on some of the tech communities part, they are not scheduled before
Q1 2006.
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